Vol: 56(70) No: 4 / December 2011 

Delay Locked Loop Clock Generator in Low Power VLSI IC Design
Goran S. Jovanović
University of Niš, Faculty of Electronic Engineering, A. Medvedeva 14, 18000 Niš, Serbia, phone: +381 (18) 529-660, e-mail: goran. jovanovic@elfak.ni.ac.rs
Darko B. Mitić
University of Niš, Faculty of Electronic Engineering , A. Medvedeva 14, 18000 Niš, Serbia, e-mail: darko.mitic@elfak.ni.ac.rs
Mile K. Stojčev
University of Niš, Faculty of Electronic Engineering, A. Medvedeva 14, 18000 Niš, Serbia, e-mail: mile.stojcev@elfak.ni.ac.rs
Dragan S. Antić
University of Niš, Faculty of Electronic Engineering , A. Medvedeva 14, 18000 Niš, Serbia, e-mail: dragan.antic@elfak.ni.ac.rs


Keywords: low power design, frequency multiplier, PLL, DLL, jitter

Abstract
In order to decrease the power consumption of embedded systems, the power management unit (PMU) is used. PMU is responsible for coordinating many functions, including: monitoring power connections and battery charges, controlling power to other integrated circuits, identifies idle or low active parts of VLSI IC and to apply lower frequency clock to supply their operations, shutting down unnecessary system components when they are left idle, controlling sleep and power functions (on and off), regulating the real-time clock, etc. Basic components of PMU are [10]: threshold detector, timer and control logic. The control logic is responsible for generating control signals for clock/power switching on/off, adjusting voltage/clock frequency, etc. We consider herein one approach for synthesis of multi-frequency and multi-phase clock generator as constituent of PMU which is based on delay locked loop (DLL) control principle. Contrary to phase locked loop (PLL) control, the DLL offers a simple implementation and lower jitter in the clock signal. The clock generator is implemented in 1.2 m CMOS technology using dedicated delay oriented design methodology. It converts a square wave signals to in-phase, quadrature-phase and eight-phase square wave signals, and multiplies the frequency by two- and four-times. The output frequency of the multi-frequency and multi-phase clock generator extends from 20MHz to 80MHz.

References
[1] J. Monteiro, S. Devades, “Computer-Aided Design Techniques for Low Power Sequential Logic Circuits”, Kluwer Academic Pub., Boston, 1997.
[2] Benini L. et al., “A Survey of Design Technique for System-Level Dynamic Power Management”, IEEE Tran. on VLSI System, vol. 8, No. 3, pp. 299-316, June 2000.
[3] K. Seno, “Implementation – Level Impact on Low Power Design”, pp. 19.1-19.10, in The Computer Engineering Handbook, ed. by Oklobdžja, CRC Press, Boca Raton, 2002.
[4] H. Varadarajan, et. al., “Low Power Design Issues”, pp. 14.11-14.21, in The Computer Engineering Handbook, ed. by V. Oklobdžija, CRC Press, Boca Raton, 2002.
[5] G. Lakohininarayana, A. Raghunathan, N. K. Iha, S. Dey, “Power Management in High-level Synthesis”, IEEE Trans. on Very Large Scale Integration System, vol. 8, No. 3, pp. 299-316, June 2000.
[6] R. Yamaguchi et al., “A 2.56GHz Four-Phase Clock Generator with Scalable No-feedback Loop Architecture”, IEEE Journal of Solid State Circuits, vol. 36, No. 11, pp. 1666-1672, November 2001.
[7] N. A. Kurd, et al., “A Multigigaherze Clocking Scheme for The Pentium 4 Microprocessor”, IEEE Journal of Solid State Circuits, vol. 36, No. 11, pp. 1647-1653, November 2001.
[8] G. Chien, “Low-Noise Design Techniques using a DLL- based Frequency Multiplier for Wireless Application”, Ph. Thesis, University of California, Berkeley, 2000.
[9] G. Chien and P. R. Gray, “A 900-MHz Local Oscillator Using a DLL-Based Frequency Multiplier Technique for PCS Applications”, Journal of Solid State Circuits, vol. 35, No. 12,pp. 1996-1999, December 2000.
[10] T. Simunic, L. Benini, P. Glynn, G. De Micheli, “Dynamic power management for portable systems”, MobiCom '00 Proceedings of the 6th annual international conference, pp. 11-19, 2000.
[11] G. Jovanović, M. Stojčev, “Low-Power Design trough Multi-Phase and Multi–Frequency Clock“, ICEST 2002, vol. 1, pp. 77-80, Niš, Oktobar 2002.

  


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